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ADARIO DATA BLOCK FIELD DEFINITIONS ADARIO DATA BLOCK FIELD DEFINITIONS ADARIO DATA BLOCK FIELD DEFINITIONS SUMMARY SUBMUX DATA FORMAT FIELD DEFINITIONS SUBMUX DATA FORMAT FIELD DEFINITIONS SUMMARY The details of the ADARIO data block format are provided in figure G-1 and in the ADARIO data format field summary. As shown in figure G-1, the eight session header words are the first eight words of the block. The channel packet for the highest priority (priority 1) channel is next, followed by the next lower priority channel packet (priority 2). Following the lowest priority channel, fill data consisting of all ones are inserted as required to complete the 2048-word data block. Within the channel packet, the first five words are the channel header words including the partial word (PW). Following the channel header is the variable size channel data field. The channel data are organized in a last-in-first-out (LIFO) fashion. The first samples acquired in the block time interval appear in the last data word of the channel packet. The sample data are formatted into the 24-bit data word such that the first sample occupies the MSBs of the word. The next sample is formatted into the next available MSBs and so on until the word is full. As an example, data formatted into 8-bit samples is shown in figure G-2. In cases where the 24-bit data word is not a multiple of the sample size, the sample boundaries do not align with the data words. In these cases, the samples at the word boundaries are divided into two words. The MSBs of the sample appear in LSBs of the first buffered word and the LSBs of the sample appear in the MSBs of the next buffered word. Since the channel data appears in a LIFO fashion in the ADARIO data block, the MSBs of the divided sample will occur in the data word following the word containing LSBs of the sample. Figure G-3 depicts ADARIO timings. |
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ADARIO Data Format Field Definitions Summary
1. Block Length - (2048 words, 24-bit words, fixed length) 2. Session Header - (8 words, fixed format) |
| SHWO | (bits 23 to 0) | SYNC Field, bits 0-23 of the 29-bit
block sync. The LSBs of the block sync are 36E19C and are contained here.
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| SHW1 | (bits 23 to 19) | SYNC Field, bits 24-28 of the 29-bit block
sync. The MSBs of the block sync are 01001 and are contained here. The
29-bit block sync is fixed for all ADARIO configurations and chosen for
minimal data cross correlation. |
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| (bits 18 to 0) | MC, Master Clock, a 19-bit binary value in
units of 250 Hz. MC is the clock frequency used to derive session and per
channel parameters. |
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| SHW2 | (bits 23 to 0) | BLK#, ADARIO Data Block Number, a 24-bit
binary value. BLK# is to zero at the start of each session and counts
up consecutively. Rollover is allowed. |
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| SHW3 | (bits 23 to 0) | YYMMDD, Time Code Field, a BCD representation
of the year (YY), month (MM), and day (DD). YYMMDD Time Code Field is
updated during the record process once per second. |
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| SHW4 | (bits 23 to 0) | HHMMSS, Time Code Field, a BCD representation
of the hour (HH), minute (MM), and second (SS). The HHMMSS Time Code
Field is updated during the record process once per second. |
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| SHW5 | (bits 23 to 0) | BMD, Block Marker Divisor, a 24-bit binary
value. BMD is established so that the block marker frequency, BM, may be
derived from MC by BM = MC/BMD |
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| SHW6 | (bit 23) | MCS, Master Clock Source, a 1-bit flag. 1 = MC was generated internally. 0 = MC was provided from an external source. |
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| (bits 22 to 19) | Q, Number of active channels minus one, a
4-bit binary value. For example, 0 indicates that one channel is active.
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| (bits 17 to 18) | SP1, Spare field 1, a 2-bit field. It is set
to zero. |
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| (bits 16 to 0) | SST, Session Start Time, a 17-bit binary
value in units of seconds. The integer number of seconds represents the
session start time of day in seconds, where midnight starts with zero.
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| SHW7 | (bits 23 to 16) | User Defined, an 8-bit field. May be input
by the user at any time during a recording session. The interpretation of
this bit field is left to the user. |
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| (bits 15 to 6) | SP2, Spare field 2, a 10-bit field. It is set
to zero. |
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| (bits 5 to 0) | VR, Version number, a 6-bit binary value. Each
update of the ADARIO format will be identified by a unique version
number. |
| 3. Channel ‘n’ Header | All channel headers contain five
24-bit ADARIO words with the following fixed format. The first logical
channel, n=1, has the highest priority and its channel packet starts in
the ninth word of the data block. Each active channel is represented by
a channel packet that is present in the data block. The logical channel
number, n, represents the relative priority of the channel and the order
in which it appears in the data block. |
| CnHW0 | (bits 23 to 20) | CH#, Physical Channel Number, a 4-bit
binary value. 0 to 15 represents the physical location of the channel
electronics in the ADARIO hardware. The user sees those locations labeled
from 1 to 16. |
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| (bits 19 to 16) | FMT, Format code for the channel data word, a
4-bit binary value. The format code is used to define the size of the user
data word by means of the following table: 15=24 bits 7=8 bits 14=22 bits 6=7 bits 13=20 bits 5=6 bits 12=18 bits 4=5 bits 11=16 bits 3=4 bits 10=14 bits 2=3 bits 9=12 bits 1=2 bits 8=10 bits 0=1 bit |
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| (bits 15 to 5) | WC, Word Count, an 11-bit binary value. WC is
the number of full channel data words that should be in the nth channel
packet. WC may range from 0 to 2040. A WC greater than the number of
actual words in channel packet indicates a data rate overflow, which would
occur when a low-priority channel is not provided sufficient space in the
fixed length data block as a result of an uncontrolled data rate in a
higher priority channel. |
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| (bits 4 to 0) | PWS, Partial Word Status, a 5-bit binary value.
PWS is related to the number of samples in the partial word and may range from
0 to 23. PWS shall be computed as follows: If the number of full samples in the partial word equals zero, then PWS = 0. If the number of full samples in the partial word does not equal zero, then PWS = Round Up [Unused bits In PW/Channel Sample Size]. |
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| CnHW1 | (bit 23) | IE, Channel Clock Source, a 1-bit flag. 1 = The channel clock was generated internally. 0 = The channel clock was provided from an external source. |
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| (bit 22) | DA, Data type, a 1-bit flag. 1 = The channel is operated as a digital channel. 0 = The channel is operated as an analog channel. |
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| (bit 21) | ROVR, Rate overrun in previous block, a 1-bit
flag. 1 = The nth channel packet in the previous data block experienced an overrun. 0 = The nth channel packet in the previous data block did not experience an overrun. |
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| (bit 20) | AOVR, Analog A/D Overrange in current block a
1-bit flag. 1 = The nth channel in the current data block experienced an analog-to-digital conversion overrange condition. 0 = The nth channel in the current data block did not experience an analog-to-digital conversion overrange condition. |
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| (bit 19) | NSIB, No samples in current block, a 1-bit flag.
1 = TRUE, there are no samples for the nth channel in the current block. 0 = False, there are samples for the nth channel in the current block. |
The definitions that are marked with an asterisk apply to analog channels
and to particular hardware implementations of ADARIO. For the purposes of
this standard these fields are not used.
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| (bits 18 to 0) | RATE, Channel sample rate indicator,
19-bit binary value. The interpretation of the rate value depends on the
condition of IE, the channel clock source flag. If IE = 1, then the value of rate is carried by the 16 LSBs of the rate field. Using rate, the frequency of the internal channel clock can be found by internal sample clock = (MC/RATE) -1. IF IE = 0, then rate is a 19-bit binary value in units of 250 Hz which equals the frequency of the external channel clock as provided by the user at the time of the setup. |
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| * | CnWD2 | (bits 23 to 16) | FB, Filter Bandwidth, an 8-bit binary value.
The formula for the bandwidth, BW, of the anti-aliasing filter used in an
analog channel incorporates FB as BW = (FB/2) X 103+FR
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| (bits 15 to 0) | TD, Time Delay to first sample, a 16-bit binary
value. TD is a measure of the time delay from the block marker, BM, to the
first sample arriving at the nth channel during the current data block
interval. TD is expressed as the number of master clock, MC, periods minus
one. |
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| * | CnWD3 | (bits 23 to 22) | FR, Filter Range, a 2-bit binary value. The
formula for the bandwidth, BW, of the anti-aliasing filter used in an
analog channel corporates FR as BW = (FB/2) X 103+FR
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| (bits 21 to 17) | ATTEN, Attenuation, a 5-bit binary value.
ATTEN represents the setting of the input attenuator (or gain) on the nth
channel at the time that the record was formed 0 = -15dB and 31 = +16dB with
intermediate settings expressed in one dB steps. |
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| (bit 16) | DCAC, Analog signal coupling, a 1-bit flag.
1 = The channel is operated with dc coupling at the input. 0 = The channel is operated with ac coupling at the input. |
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| (bits 15 to 8) | CHP, Channel Parameter field, an 8-bit field.
The interpretation of the CHP field depends upon the card type with which
it is associated, as defined by the CHT field. Each card type established
by the CHT field, as part of its definition, shall specify the form and
interpretation of the CHP field. To date, four input card types have been
established. The following CHP fields are defined as |
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* (bits 15 to 8) |
For CHT=0 remain undefined for the present analog single channel implementation except that the present hardware implementation expects an all zero field. Would be subject to future definition as long as all the zero fill is set aside. |
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* (bits 15 to 8) |
For CHT=1 remain unused for the present digital single channel implementations except that the present hardware implementation expects an all zero field. Would be subject to future definition as long as the all zero fill is set aside. |
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* (bits 15 to 8) |
For CHT=2 remain unused for the present dual-purpose channel implementations except that the present hardware implementation expects an all zero field. Would be subject to future definition as long as the all zero fill is set aside. |
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(bits 15 to 12) |
For CHT=3 establish the number of subchannels that are multiplexed into the multichannel data carried by the nth channel. |
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| (bits 11 to 8) | identify the subchannel number of the first
sample contained in the nth channel packet of the data block.
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| (bits 7 to 6) | SP3, Spare field 3, a 2-bit field. It is set
to zero. |
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| (bits 5 to 0) | CHT, Channel Type, a 6-bit field. Defines
the type of channel through which input data was acquired. Additional
channel types to be defined by future users and developers.
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| * | CHT=0 Single channel analog input | ||
| * | CHT=1 Single channel digital input | ||
| * | CHT=2 Single channel, dual-purpose, analog or digital input | ||
| * | CHT=3 Multichannel analog input capable of multiplexing up to 16 analog inputs | ||
| * | CHT=4 Single channel digital input, dual
channel analog input (stereo) “L” Channel on bits 15 to 8 of the sample word, “R” channel on bits 7 to 0 of the sample word |
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| * | CHT=5 Single channel, triple-purpose,
analog, digital, submux, formatted input |
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| CnWD4 | (bits 23 to 0) | PW, Partial Word, A 24-bit field. PW contains
the last samples of the data block. The most significant bits of word
contain the first sample, followed by the next sample in the next most
significant bits. The number of samples in the PW is defined in the PWS
field. The unused bits are not intentionally set and so contain random
data. |
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| Fill | (bits 23 to 0) | Fill, Fill Words consisting of all ones
binary, used for fixed rate aggregate. Fill words may be omitted when
variable rate aggregate can be accommodated resulting in variable length
blocks of up to 2048, 24-bit words. |